DK-DEV-5SGXEA7N【PDF 78/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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4-8

Types of Clock Regions

Figure 4-9: Hierarchical Clock Networks in Each Spine Clock Per Quadrant

SV51005

2014.01.10

Clock output from the PLL

that drives into the SCLKs.

9

Column I/O clock: clock that drives

the column I/O core registers and I/O interfaces.

GCLK

PLL Feedback Clock

PCLK

RCLK

16

5

88

23

SCLK

33

2

Core reference clock: clock that feeds

into the PLL as the PLL reference clock.

There are up to 88 PCLKs that

can drive the SCLKs in each

spine clock in the largest device.

6

Row clock: clock source to the LAB,

memory blocks, and row I/O interfaces

in the core row.

There are up to 23 RCLKs that

can drive the SCLKs in each spine

clock in the largest device.

Types of Clock Regions

This section describes the types of clock regions in Stratix V devices.

Entire Device Clock Region

To form the entire device clock region, a source drives a signal in a GCLK network that can be routed through

the entire device. The source is not necessarily a clock signal. This clock region has the maximum insertion

delay when compared with other clock regions, but allows the signal to reach every destination in the device.

It is a good option for routing global reset and clear signals or routing clocks throughout the device.

Regional Clock Region

To form a regional clock region, a source drives a signal in a RCLK network that you can route throughout

one quadrant of the device. This clock region provides the lowest skew in a quadrant. It is a good option if

all the destinations are in a single quadrant.

Dual-Regional Clock Region

To form a dual-regional clock region, a single source (a clock pin or PLL output) generates a dual-regional

clock by driving two RCLK networks (one from each quadrant). This technique allows destinations across

two adjacent device quadrants to use the same low-skew clock. The routing of this signal on an entire side

has approximately the same delay as a RCLK region. Internal logic can also drive a dual-regional clock

network.

Altera Corporation

Clock Networks and PLLs in Stratix V Devices

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